The rise in the popularity of new forms of communication systems such as the Internet has driven the need for network systems that offer greater and greater amounts of bandwidth and data control means. Prior to the explosion of the Internet's popularity, most telecommunications systems were designed with an architecture to support primarily a single service (e.g. voice calls). Today, the newer telecommunication systems must be designed for the larger bandwidth demands and data control means. These newer systems and networks must be able to provide two way synchronized transfer of video, audio and other data.
Phase locked loops are frequently used in two-way data communication systems, to generate an output clock derived from the input data. Conventionally, a phase locked loop includes a voltage controlled oscillator which provides an output frequency to serve as the clock signal. The phased locked loop uses an input data signal in conjunction with the voltage controlled oscillator to generate the output clock signal. The output clock signal can then regulate the output timing of output data signals between data processing devices and data transmitters for transmittal of data further along a data communication system.
If the input data signal is lost or interrupted then an output frequency of the voltage-controlled oscillator will generally swing to one voltage rail or the other resulting in a loss of an accurate output clock signal and potential loss of data through the communication system. To prevent the output frequency of the voltage-controlled oscillator from swinging to one voltage rail or the other some prior art systems substitute a second synchronization source or system clock to provide the synchronization for the system. For example, in the prior art, the loss of an input data signal to the phased locked loop will cause the phase locked loop to switch to a fixed voltage reference, such as substitute, fixed voltage-controlled oscillator. The problem with this prior art method is that the fixed voltage reference of the substitute voltage-controlled oscillator may be and often is significantly different from the clock frequency at which the phased locked loop was locked just prior to the input data loss. In this case, the system can still experience significant problems in that the rapid switching from one clock frequency to another will likely cause data errors.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for systems and methods for improved hold-over capability in phased locked loops to account for momentary breaks in an input communication channel.